FPGA design of low complexity SEFDM detection techniques

This paper presents for the first time the hardware design of low complexity detection algorithms for the recovery of Spectrally Efficient Frequency Division Multiplexing (SEFDM) signals. The work shows that a practical design is feasible using Field Programmable Gate Arrays (FPGAs). Two detection techniques can be implemented using the proposed system architecture, namely Zero Forcing (ZF) and Truncated Singular Value Decomposition (TSVD), demonstrating that our hardware design is flexible. TSVD offers a significant reduction in complexity compared to optimal detection techniques, such as Maximum Likelihood (ML) while outperforming ZF, in terms of Bit Error Rate (BER). Results show excellent fixed-point performance and are comparable to existing floating-point computer-based simulations.